Conventional OCD circuitry comprises an output control circuit (e.g., a tristate circuit) for driving data over a signal network such as a data bus and for placing the OCD circuitry in a high impedance state or in "tristate" to allow other devices access to the signal network. To couple the output control circuit to a signal network, the OCD circuitry further comprises output drive devices (e.g., pull-up and pull-down transistors) that drive data from the output control circuit over the signal network, and that place the OCD in tristate when disabled by the output control circuit.
OCD circuitry employing a split rail power supply typically includes a first power rail for supplying a first voltage to the output control circuit and a second power rail for supplying a second voltage to the output drive devices. As a consequence of the output control circuit being powered by a separate power rail (e.g., the first power rail), when a plurality of devices having OCD circuitry are coupled to a signal network, high current conditions can result within the signal network that damage the devices (i.e., deleteriously high current conditions) when the first power rail is at a low voltage (e.g., at power-on or due to a hardware failure) while the second power rail (e.g., the power rail that powers the output drive devices) is at its normal operating voltage (i.e., high) as described below with reference to FIG. 1.
FIG. 1 is a schematic diagram of a signal network 101 having three memory chips 103a-c connected thereto. Each memory chip 103a-c comprises an output control circuit 105a-c and output drive devices 107a-c connected to the output control circuit 105a-c and to the signal network 101 as shown. The output drive devices 107a-c of each memory chip 103a-c comprise a pull-up p-channel metal-oxide-semiconductor field-effect transistor (PFET) 109a-c and a pull-down n-channel metal-oxide-semiconductor field-effect transistor (NFET) 111a-c. The output control circuits 105a-c are powered via a first power rail (VDD) and the output drive devices 107a-c are powered via a second power rail (V.sub.DDQ)
During normal operation, only one of the memory chips 103a-c at a time drives data over the signal network 101, and the remainder of the memory chips are placed in tristate (e.g., by disabling each memory chip's output drive devices). However, if the first power rail (V.sub.DD) is low (e.g., at power-on or due to a hardware failure) while the second power rail (V.sub.DDQ) is high, the output state of each output control circuit 105a-c is unknown, more than one memory chip 103a-c may drive data over the signal network 101 and a deleteriously high current condition may result that damages one or more of the memory chips 103a-c. For example, if the pull-up PFET 109a of the first memory chip 103a is ON while the pull-down NFET 111c of the third memory chip 103c is ON, a high current path exists between the second power rail (V.sub.DDQ) and ground that produces a deleteriously high current (I.sub.DEL) as shown. The current I.sub.DEL may damage both the first and the third memory chips 103a, 103c if sufficient in magnitude. Accordingly, a need exists for a method and apparatus for protecting OCD circuitry employing a split rail power supply from deleteriously high current conditions.